The inception of high quality gallium-nitride based crystal growth has led to growing popularity in the use of light emitting diodes (LED) in general lighting and backlighting applications to replace conventional light sources such as incandescent bulbs, halogen bulbs, cold cathode fluorescent lamps (CCFL) and compact fluorescent lamps (CFL). For these applications, indium gallium nitride-based blue LED chips emitting at ˜450 nm is typically used to excite a phosphor layer to create white light. Although rapid progress has been made over the past 10 years in the optimizing of gallium nitride growth and device structure, p-electrode ohmic contact resistance and light extraction efficiency (LEE) remain the major obstacles in limiting the performance of these devices. Reducing the p-electrode contact resistance is intrinsically difficult due to the wide bandgap nature (3.4 eV) and low hole mobility (μH˜10 cm2/Vs) of gallium nitride. The contact resistance is governed by the quality of the contact between the metal electrode and semiconductor interface, and also the contact area. For small LED chip manufacturers, p-electrode contact resistance is particularly problematic, since the LED chip size is typically only ˜200×600 um and high contact resistance is a major limitation to the wall plug efficiency of the device.
Due to the large refractive index contrast between gallium nitride (n˜2.5) and air, much of the light generated in the active region is confined and waveguided within the semiconductor layers, thus unable to escape to air. As a result, the waveguided light is eventually absorbed, leading to poor LEE. The light extraction efficiency for a conventional planar LED chip is typically only ˜25-30%. A variety of methods has been employed to increase LEE, such as surface roughening, photonic crystals, flip-chip, chip shaping, and patterned sapphire substrates. The use of patterned sapphire substrates as extraction features is a common method to improve LEE in commercial blue LED chips, which leads to LEE values of ˜60% (Yamada et. al, Japanese Journal of Applied Physics, vol. 41, L1431-1433, (2002)). However, growth on patterned sapphire substrates is not easy, and uniformity is particularly problematic on larger wafers (e.g., 6 inch).
In general, the extraction features are preferably placed as close as possible to the active region in order to achieve the best LEE. Matioli et. al [Applied Physics Letters, vol. 96, pp. 031108 (2010)] employed embedded air-gap photonic crystal structures and achieved an extraction efficiency of ˜73% when un-encapsulated and 94% when encapsulated.
Horng et. al [Applied Physics Letters, vol. 86, 221101 (2005)] reported the use of a roughened ITO layer to increase LEE, but the extraction features are positioned far away (˜500 nm) from the active region, reducing light extraction efficiency. Furthermore, roughened surfaces are usually difficult to control in volume manufacturing.
FIG. 1 is the schematic diagram of a two dimensional periodic variation of dielectric constant structure 512 used to increase LEE as described by U.S. Pat. No. 5,955,749 (J. Joannopoulos et al., issued 21 Sep. 1999). In the example given, the periodic structures 512 are formed in the p-type GaAs 506 layer by etching to improve LEE. While this structure leads to improved LEE, it also results in increased lateral current spreading resistance and p-electrode ohmic contact resistance due to etch damage to the p-layer induced by the dry-etching process.
FIG. 2 is an embodiment of an LED device structure described in US 2010/0059779 A1 (D. Chen et al., published 11 Mar. 2010). Dielectric layers 602 are embedded within the active region 108 vicinity to improve LEE. The p-type layer 610 is regrown over the embedded dielectric layers 602 to planarise the surface. While LEE can be improved with this structure, the p-contact resistance will remain high as the p-electrode contact area is the same as a conventional planar LED.
FIG. 3 shows an LED device structure 50 disclosed in US 2008/0279242 A1 (D. Bour, published 13 Nov. 2008). A regrowth method is used to embed SiO2 structures 58 within the p-GaN region 59. The final device structure is planarised. Similar to the previous example, the p-contact resistance will remain high since the contact area is similar to conventional planar LEDs.
FIG. 4 is an LED device structure 300 disclosed in U.S. Pat. No. 7,244,957 B2 (N. Nakajo et al., issued 17 Jul. 2007). A micrometer-scale light projection region 150 consisting of GaN material is formed on the p-surface either by etching through ITO layer or by patterning SiO2 layers, to improve light extraction efficiency. Current spreading may be an issue with micrometer-scale structures and the light extraction features are placed further away from the active region, therefore reducing its effectiveness.
FIG. 5 depicts an embodiment of an LED device disclosed in U.S. Pat. No. 6,091,085 (S. Lester, issued 18 Jul. 2000). Using conventional lithography techniques, GaN is regrown on patterned SiO2 layers to form light projection regions 24 as means to increase light extraction efficiency.
Thus, there is a need in the art for LED devices for good light extraction efficiency, but also to improve the p-electrode contact resistance. An object of the present invention is to provide an LED with good light extraction efficiency, and simultaneously increasing the p-electrode contact area, thereby improving ohmic contact resistance. Both these features are key towards realization of high efficiency nitride LEDs.